A Flip-Flop Matching Engine to Verify Sequential Optimizations

Equivalence checking tools often use a flip-flop matching step to avoid the state space traversal. Due to sequential optimizations performed during synthesis (merge, replication, redundancy removal, ...) and don't care conditions, the matching step can be very complex as well as incomplete. If the matching is incomplete, even the use of a fast and efficient SAT solver during the combinational equivalence-checking step may not prevent the failure of this approach. In this paper, we present a flip-flop matching engine, which is able to verify optimized circuits and handle don't care conditions

A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators

International audience3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 μm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs

A Survey on Security Threats and Countermeasures in IEEE Test Standards

International audienceEditor's note: Test infrastructure has been shown to be a portal for hackers. This article reviews the threats and countermeasures for IEEE test infrastructure standards

Differential Power Analysis against the Miller Algorithm

Article en cours de publicationPairings permit several protocol simplications and original scheme creation, for example Identity Based Cryptography protocols. Initially, the use of pairings did not involve any secret entry, consequently, side channel attacks were not a threat for pairing based cryptography. On the contrary, in an Identity Based Cryptographic protocol, one of the two entries to the pairing is secret. Side Channel Attacks can be therefore applied to nd this secret. We realize a Differential Power Analysis(DPA) against the Miller algorithm, the central step to compute the Weil, Tate and Ate pairing. Keywords: Pairing, Miller Algorithm, Pairing Based Cryptography, SCA, DPA

Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits

International audienceAmong all means to attack a security dedicated circuit, fault injection by means of laser illumination is a very efficient one. The laser beam creates electrons/holes pairs along its way through the silicon. The collection of these charges creates a transient current and thus may induce a fault in the circuit. Nevertheless the collection efficiency depends on various parameters including the technology used to implement the circuit. Here, up-to-date Bulk and Fully Depleted Silicon on Insulator (FD-SOI) 28nm technologies are compared in terms of sensitivity against laser injection. It comes out that FD-SOI structures show less sensitivity to laser injection and thus should be further explored for security dedicated circuits implementations

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection

International audienceBulk Built-In Current Sensors (BBICSs) are able to detect anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. This paper presents a new strategy to design BBICSs with optimal transient-fault detection sensitivity while keeping low both area and power overheads. The approach allows increasing the detection sensitivity by setting an asymmetry in the flipping ability of the sensor's latch. In addition, we introduce a mechanism to tune the delay of the bulk access transistors that improves even more the BBICS detection sensitivity. The proposed design strategy offers a good compromise between fault detection sensitivity and power consumption; moreover it makes feasible the use of several CMOS processes

A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults

International audienceThis work proposes a novel built-in current sensor for detecting transient faults of short and long duration as well as multiple faults in combinational and sequential logic. Unlike prior similar strategies, which are formed by pairs of PMOS and NMOS sensors, the proposed scheme is a single sensor connected to PMOS and NMOS bulks of the monitored logic. In comparison with existing transient-fault mitigation techniques, the paper presents very competitive results that indicate no performance penalty, and overheads of only 26 % in power consumption and 23 % in area

Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts

International audienceBulk Built-In Current Sensors (BBICS) are fault detection mechanisms embedded in integrated systems. BBICS are able to monitor anomalous transient currents like the so-called single event effects induced by radiation or even malicious injection sources. This work reviews BBICS principles and introduce new sensor architectures that improve the transient-fault detection sensitivity. In addition, a test chip is presented for the validation of the sensor concept under the laser-induced effects

Compression de données pour le test des circuits intégrés

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF